With continuous development of semiconductor technology, sizes of semiconductor devices are scaling down, so are the sizes of semiconductor devices' components. Taking a MOS transistor as an example, the MOS transistor's overall structure shrinks and, accordingly, dimensions of the source, the drain and the gate structures also decrease, resulting in a thinner gate dielectric layer. However, if the gate electric layer is not thick enough, the breakdown voltage may be unacceptably small, and the leakage current between the gate and the channel region (namely, the gate leakage) may increase, which may cause device failure. Therefore, a gate stack including a high-k dielectric layer and a metal gate is introduced into the MOS transistor to reduce the gate leakage and improve the electrical performance. Normally, to avoid the metal material of the metal gate from undesirably affecting other components, the gate stack is formed in a “gate-last” process.
With current techniques, it is quite often that PMOS transistors and NMOS transistors are formed in a same substrate. However, the metal gates of the PMOS transistors and the NMOS transistors are different. More specifically, the work function layers of the metal gates have different parameters and structures. Therefore, in the gate-last process, the metal gates of the POMS and NMOS transistors are often formed separately.
Further, in a conventional process of CMOS transistor formation, at least two CMP processes are employed to form the metal gates, in which over polishing may occur twice. It's often difficult to anticipate the quantity of the transistors which may be undesirably over polished.
Therefore, there is a need to provide a method for forming metal gates, in which less over polishing occurs, so as to accurately control the metal gates' thickness.